{...\pwm_C.Sch (21:11, Aug-25-2020)} Components ( ("D21" "1N4007" "P1") ("D18" "1N4007" "P1") ("R3" "RR 100R" "R75") ("DT2" "PC827" "DIP8") ("D20" "1N4007" "P1") ("D17" "1N4007" "P1") ("D6" "1N4007" "P1") ("D9" "1N4007" "P1") ("R2" "RR 100R" "R75") ("D19" "1N4007" "P1") ("D16" "1N4007" "P1") ("D12" "1N4007" "P1") ("D15" "1N4007" "P1") ("R5" "RR 100R" "R75") ("T12" "BC547C" "TO92") ("R23" "RR 4k7" "R75") ("D5" "1N4007" "P1") ("D8" "1N4007" "P1") ("D11" "1N4007" "P1") ("D14" "1N4007" "P1") ("T11" "BC547C" "TO92") ("R22" "RR 4k7" "R75") ("D4" "1N4007" "P1") ("D7" "1N4007" "P1") ("D10" "1N4007" "P1") ("D13" "1N4007" "P1") ("DT1" "PC847_" "DIP16") ("T10" "BC547C" "TO92") ("R21" "RR 4k7" "R75") ("cpu1" "89C2051" "DIP20") ("T9" "BC547C" "TO92") ("R20" "RR 4k7" "R75") ("D24" "1N4006" "P1") ("L298" "J1.16_" "S1G16") ("T2" "FET N ENHC" "TO92") ("R30" "RR 10k" "R75") ("C3" "C 22J" "CK25B") ("D25" "1N4006" "P1") ("xtal" "XTAL 3MHz" "XHC18V") ("T5" "BC547C" "TO92") ("R11" "RR 1k" "R75") ("R111" "RR 10k" "R75") ("C4" "C 22J" "CK25B") ("D1" "D" "P1") ("T6" "BC547C" "TO92") ("R12" "RR 1k" "R75") ("R112" "RR 10k" "R75") ("R17" "RRA 8 10k" "S1G9") ("R8" "RR 1K" "R75") ("D2" "D" "P1") ("T7" "BC547C" "TO92") ("R13" "RR 1k" "R75") ("R113" "RR 10k" "R75") ("D3" "D" "P1") ("DT4" "PC817" "DIP4") ("R6" "RR 1J" "R75") ("R16" "RR 100" "R75") ("C7" "C POL" "CR50") ("R1" "R 10K" "R75") ("R4" "R TRIM 50J" "64Y") ("C2" "C POL 2M2" "CR50") ("C5" "C POL 100M" "CR50") ("C105" "C POL 100M" "CR50") ("DT3" "PC817" "DIP4") ("U1" "78T05" "TO92") ("T1" "IRF9530" "TO220") ("D22" "1N4007" "P1") ("R7" "RR 10k" "R75") ("D23" "1N4007" "P1") ) Netlist ( ("cpu1" 10 "DT1" 13 "DT1" 15 "DT1" 9 "DT1" 11 "DT2" 5 "DT2" 7 "D24" 2 "L298" 1 "L298" 8 "DT3" 3 "L298" 15 "T2" 1 "C3" 1 "C4" 1 "DT4" 3 "R1" 2 "T5" 1 "D1" 2 "R11" 2 "T6" 1 "D2" 2 "R12" 2 "T7" 1 "D3" 2 "R13" 2 "C5" 2 "C105" 2 "U1" 2 "T9" 1 "T10" 1 "T11" 1 "T12" 1 "cpu1" 10) {GND} {|0|} ("D21" 2 "R3" 2 "D18" 1) {|0|} ("D21" 1 "D20" 2 "D18" 2 "D17" 1) {|0|} ("R3" 1 "DT2" 2 "DT2" 3) {|0|} ("D19" 1 "D10" 1 "DT1" 4 "DT1" 1 "D13" 2 "D4" 1 "DT1" 8 "DT1" 5 "D7" 2 "L298" 3 "L298" 2 "D24" 1 "D25" 2 "D16" 2 "DT2" 1 "DT2" 4) {|0|} ("DT2" 6 "DT2" 8 "cpu1" 11) {|0|} ("D20" 1 "D19" 2 "D17" 2 "D16" 1) {|0|} ("D6" 2 "R2" 2 "D9" 1) {|0|} ("D6" 1 "D5" 2 "D9" 2 "D8" 1) {|0|} ("R2" 1 "DT1" 6 "DT1" 7) {|0|} ("D12" 2 "R5" 2 "D15" 1) {|0|} ("D12" 1 "D11" 2 "D15" 2 "D14" 1) {|0|} ("R5" 1 "DT1" 2 "DT1" 3) {|0|} ("cpu1" 12 "R17" 9 "T12" 2) {|0|} ("T12" 3 "R23" 2) {|0|} ("R23" 1 "R22" 1 "R21" 1 "R20" 1 "U1" 1 "C105" 1 "D22" 1) {|0|} ("DT1" 10 "DT1" 12 "cpu1" 9) {|0|} ("DT1" 14 "DT1" 16 "cpu1" 8) {|0|} ("D5" 1 "D4" 2 "D8" 2 "D7" 1) {|0|} ("D11" 1 "D10" 2 "D14" 2 "D13" 1) {|0|} ("cpu1" 13 "R17" 8 "T11" 2) {|0|} ("T11" 3 "R22" 2) {|0|} ("cpu1" 14 "R17" 7 "T10" 2) {|0|} ("T10" 3 "R21" 2) {|0|} ("T2" 2 "L298" 7 "L298" 5 "cpu1" 7) {|0|} ("DT4" 4 "cpu1" 6) {|0|} ("C3" 2 "xtal" 1 "cpu1" 5) {|0|} ("xtal" 2 "C4" 2 "cpu1" 4) {|0|} ("L298" 6 "cpu1" 3) {|0|} ("L298" 11 "cpu1" 2) {|0|} ("cpu1" 1 "R1" 1 "C2" 2) {|0|} ("cpu1" 15 "T9" 2 "R17" 6) {|0|} ("cpu1" 16 "T5" 3 "R17" 5) {|0|} ("cpu1" 17 "T6" 3 "R17" 4) {|0|} ("cpu1" 18 "T7" 3 "R17" 3) {|0|} ("cpu1" 19 "R8" 2 "R17" 2) {|0|} ("cpu1" 20 "cpu1" 20 "R17" 1 "R17" 1 "R17" 1 "R17" 1 "R17" 1 "R17" 1 "R17" 1 "R17" 1 "DT3" 1 "L298" 9 "R30" 2 "C2" 1 "U1" 3 "C5" 1) {VCC} {|0 |} ("T9" 3 "R20" 2) {|0|} ("L298" 13 "L298" 14) {|0|} ("T2" 3 "R30" 1 "L298" 10 "L298" 12) {|0|} ("D25" 1 "DT4" 2 "C7" 2 "R16" 2 "R6" 2 "L298" 4) {|0|} ("T5" 2 "R111" 2 "R11" 1 "D1" 1) {|0|} ("T6" 2 "R112" 2 "R12" 1 "D2" 1) {|0|} ("R8" 1 "DT3" 2) {|0|} ("T7" 2 "R113" 2 "R13" 1 "D3" 1) {|0|} ("DT4" 1 "R4" 3 "R16" 1 "R4" 2 "C7" 1) {|0|} ("R6" 1 "R4" 1 "T1" 2) {|0|} ("T1" 1 "R7" 2 "DT3" 4) {|0|} ("T1" 3 "D23" 1 "R7" 1) {|0|} ) { Non-connected IN pins ( ) Non-connected OUT pins ( ) Non-connected I/O pins ( ) Non-connected OC pins ( ) Non-connected OE pins ( ) Non-connected PAS pins ( ("L298" 16) ("R111" 1) ("R112" 1) ("R113" 1) ("D22" 2) ("D23" 2) ) Non-connected HIZ pins ( ) Non-connected POWER pins ( ) Errors ( ) }